CPE 315
Professor Stearns
fall 2004
Laboratory #6 - MIPS cpu phase 1
Part A counts as 1 lab; Part B is mandatory and counts as 4 labs.
Part A due Wed, 10/20 by the end of lab.
Part B due Wed, 10/27 by the end of lab.

1. You may use SIM or Xilinx for this laboratory.
2. You may do Part A with a partner.
3. Part B is is an individual assignment; all submission and plagiarism rules are in effect.
   Except: you may implement the ALU and the test romfile with your partner.
   Note: see special rules for Xilinx users.
   
4. You may post your screen prints on your web page instead of printing them.
   Please clearly identify each screen print and describe what it contains.
   

• acquaint you with the MIPS fetch circuit (fig. 5.6 in textbook)
• do phase #1 of building your own cpu.
• practice the design of proper test cases for a system.

Fetch Circuit
clock signature
clock implementation
fetch unit signature
fetch unit implementation
fetch unit test
sample machine code file (Note: one word per line)
makefile

1. Create a machine code file that contains your full name in ascii.
   The format must be identical to the sample file; blank fill the last word if
   size(your name) mod 4 != 0
   

2. Build and operate the fetch circuit.
   The fetch circuit works as provided; you need not make any changes.
   The machine code file shows the expected input format.
   Load your name into the instruction memory and use the fetch circuit to read each word.
   

3. Xilinx Users
   You must build your own fetch circuit; ensure that it matches Fig. 5.6 and also initializes the PC to 8.
   

1. screen prints displaying your name words on the fetch output; show the hex digit for each group of 4 bits and letter for each byte.
   Do this for both partners if you're working with another person.
   
2. a clear hand-drawn circuit diagram of the fetch circuit (similar to fig 5.)
   
3. Xilinx Users
   ModelSim output that demonstrates your fetch circuit is working.
   

Part B Description

1. ALU extension
   You must extend your ALU to the complete MIPS ALU as shown in Fig. B.5.12. (except you may omit Zero for now)
   You may complete the MIPS alu with your partner.
   

2. Build and operate the following subset of Fig. 5.15
       Fetch unit (subset required to do PC = PC + 4)
       Registers (use switch for RegWrite)
       AluSrc Mux (use switch for control line)
       Sign extend (design this as a module)
       ALU (your ALU extended to handle SLT instruction)
   

3. The goal of this lab: get the correct ALU output.
   Build your cpu to handle 32 bits.
   

4. Write a test romfile that includes a rich set of test cases.
   The test cases should first ensure that some MIPS registers get loaded.
   Then the test cases should fully test each circuit.
   You may collaborate with your partner on the creation of this test romfile;

   Write the test cases in XSPIM and then create the romfile by hand.
   Unfortunately, there is no way to export MIPS machine code from XSPIM to a romfile; it must be done by hand.

5. Xilinx Users
   Because SIM users are provided with Muxes and Registers, you may design and implement those circuits with a partner.
   

Part B Deliverables

1. Source listings of your simulation files; you must use a module for the Sign extend.
   

2. A MIPS assembly listing that corresponds to your romfile.
   

3. A listing of your romfile.
   

4. A few selected screen prints that prove your simulation loads some MIPS registers and works correctly.
   You must include on your display:
       Instruction[31-0]
       PC[31-0]
       ALU result[31-0]
   

5. A demonstration, in lab, using a romfile to be developed by Prof. Stearns
   

6. You must use the following keys for your switches:
   

   AluSrc	a
   RegDst	d
   RegWrite	w
   ALU operation	uiop for A invert, B negate and Operation
   Write Data	3210 for bits 3-0 only (you can ignore other bits)

7. Xilinx Users
   Create ModelSim tests that demonstrate all of possible instructions in Fig. 5.11. You may either demo your circuit during lab time or you may submit a fully annotatted and complete ModelSim printout.