CPE 315
Professor Stearns
fall 2004
Lab #6 FAQ

1. What components should be shown on the hard-drawn figure?
   All of them: Mux, Register, Adder, Rom
   and the connections between them.

2. How should we build the Registers?
   Don't. Use the SIM RegisterFile; it works fine. There is a nice example in the SIM apis.
   

3. What are the A and B busses?
   They refer to the ALU data inputs; these are universally known as the A and B busses.
   

4. How do I build the Control Unit and the ALU Control?
   For now, use switches. Your brain is the control unit until Lab 7.
   Suggestion: put control signal values on each line in your assembly code

5. What is collaboration?
   See the syllabus. You may talk about the lab but even a single line of common SIM code will be considered cheating.
   

6. Zero output - Does Lab 6b have to include the Zero output?
   No.
   

7. Which instructions does Lab 6b support?
   You must support the relevant actions of the following instructions; since this is a partial CPU implementation, it doesn't support the whole instruction.
   add, sub, addi, addu, subu, addiu, and, or, andi, ori, lw, sw, slt
   

8. Xilinx Question - How do we put instructions in the Instruction Memory?
   You can initialize memory with direct statements in VHDL (easy) or by reading a file in VHDL (difficulty unknown).
   If you prefer, you can skip the Instruction Memory and enter Instructions directly into ModelSim (easy but tedious).
   

9. Xilinx Question - Are there any schematic capture Muxes that take a bus as input?
   Apparently no.
   You are welcome to colloborate with your partner to build a bus-input bus.
   Suggestion: build one Mux module that takes four 32-bit busses as input and use it for all Mux applications.