CPE 315
Fall 2004
Lab #7 FAQ
- Do I have to worry about overflows?
Not in this lab.
- How do I see inside the register file?
The SIM register file supports > 2 read ports.
Add a 3rd read port with switches to drive Read register 3 and
probes to view Read data 3. Then you can display any register
at any time.
Note: this technique is required in lab 7
- How do I see inside RAM?
You can use the same technique as for the register file but
it's not necessary.
The test program will load all results from memory to a register;
you can verify results in the register file.
- Which instructions does the control unit on in Appendix C support?
This control unit is only partially complete. Its purpose is to show
you how to build a control unit from PLAs.
- Does SIM have a PLA component?
No. But the Iand and CiOr gates make it quite easy to implement a PLA-like
structure.
- Do we have to support negative offsets in the LW/SW?
Yes.
- How big should Data memory be?
Big enough to run the test program and no bigger.
Note that the Ram address bus must be exactly == log 2 Ram size
- How about some hints on designing the instructions that don't work?
- SLTU is discussed in the midterm solutions
Control has no way of decoding R-type instructions.
Set the SLTU control bit in ALU control.
- ADDI
Control decodes the ADDI instruction and sets the control bits
appropriately.
Be sure to choose a clever ALUOp value.
- LUI
Control decodes the LUI instruction and sets the control bits
appropriately.
If you use the ALU (a design choice), choose a clever ALUOp value.
But you don't have to use the ALU for the LUI instruction.
- What is the geometry of the Control ROM?
Input: 6 bits (less if you minimize). Do not send additional
signals to Control!
Output: 16 bits, some unused
Size: 64 words (less if you minimize).
- What is the geometry of the ALU Control Rom?
Input: 8 bits or less (you should minimize). Do not send
additional signals to ALU Control! (such as Op Code)
Output: 5 bits, including SLTU (declare an 8 bit bus and leave 3 unused)
Size: 256 words if you're crazy enough not to minimize
- I read that SLT in Figures B.5.10 and B.5.12 doesn't work
Correct. If the subtraction produces an Overflow, the Set bit is
incorrect.
You don't have to worry about this in Lab 7; implement the circuit
on the midterm solutions.
Be sure you understand fully for the final exam.
- What's the difference between ADD and ADDU?
For this lab, there is no difference.
In a MIPS cpu, an overflow during an ADD will generate an exception.
- Can we use the unused code in ALUOp (11)?
No. It complicates the design and isn't necessary.
Last updated on 11/12/04