CPE 315
Professor Stearns
MIPS 32-bit CPU - Basic Principles
The MIPS cpu is a 32-bit RISC (Reduced Instruction Set Computer)
RISC means: instructions are simple; each instruction
performs a simple operation.
It requires more instructions to
accomplish what one CISC (Complex Instruction Set Computer) instruction can do.
The MIPS ISA (Instruction Set Architecture) is quite simple with
two major exceptions.
- Instructions, registers, addresses, address space are exactly 32 bits
1st major ISA problem: how do you design branch/memory access instructions that
must address 32 bits?
- Only two instructions can access memory.
Load Word (LW)
Store Word (SW)
- Each instruction uses one and only one address mode.
There are no addressing mode bits in the instruction.
- There are no condition codes at the programming level.
- MIPS is a 3 address ISA.
e.g. ADD $1,$2,$3