Design a complete SLT circuit that handles:
Set = unsigned' ^ V' ^ Result[31] // Your Lab #3 circuit
+ unsigned' ^ V ^ ???? // Finish for this exercise
+ unsigned ^ ????? // Finish for this exercise
Note: you need to add a new control signal that tells the ALU it is doing an unsigned SLT.
Recall the ALU doesn't know the difference between 2's complement and unsigned math. That principle now changes for SLT instructions.
Show your design to Prof. Stearns