CPE 315
Professor Stearns
Winter 2008
Laboratory Project #3 - MIPS cpu phase 1
Due Thursday, Feb. 14 by 3:10 pm
This laboratory is mandatory and counts as 4 labs

1. Lab Project #3 is an individual assignment; all submission and plagiarism rules are in effect.
   

• do phase #1 of building your own cpu.

Fetch Circuit
clock signature
clock implementation
fetch unit signature
fetch unit implementation
fetch unit test
makefile

1. ALU extension
   You must extend your ALU to the complete MIPS ALU as shown in Fig. B.5.11.
   

2. Build and operate the following subset of Fig. 5.15
       Fetch unit (subset required to do PC = PC + 4)
       Register File (use switch for RegWrite)
       AluSrc Mux (use switch for control line)
       Sign extend (design this as a module)
       ALU (your ALU extended to handle SLT instruction)
   

   Note: connect the ALU output directly to Write Data
   

3. Extra port on Register File
   You must add a 3rd port to the Register File (see the example in the signature file)
   Wire 5 switches to Read Register 3 and wire 32 probes to Read data 3
   This 3rd port is your best debugging tool!
   

4. Clock timing
   The SIM sequential circuits operate on the falling edge of the clock.
   You need to send an inverted clock to the Register File for proper timing.
   

5. The goal of this lab: get a partial cpu working.
   Build your alu and busses to handle 32 bits.
   

6. Testing
   Use the test program provided by Prof. Stearns
   The romfile formatter will generate the code in the proper format for SIM.
   

1. Source listings of your simulation files; you must use a module for the Sign extend.
   

2. A demonstration, in lab, using the test program developed by Prof. Stearns

3. You must use the following keys for your switches:
   

   AluSrc	a
   RegDst	d
   RegWrite	w
   ALU operation	ijop for A invert, B negate and Operation