CPE 315
Professor Stearns
Winter 2008
Laboratory #4 - MIPS cpu phase 2
Formal lab deliverable due Thursday, Feb. 28 at 3:10 pm.
This individual lab is mandatory and counts as 4 labs.

Lab 4 FAQ     Chapt. 5 name confusion
Notes:
  1. All submission and plagiarism rules are in effect for this lab and will be enforced.
  2. You may share control unit designs with your partner on Lab Exercise #5 but nothing else!

Objective: to build Fig. 5.24 + the addi, lui and sltu instructions

Files:

makefile
Test Program #1 and its machine code
Test Program #2

References
Appendix C of Patterson and Hennessy if you wish to build your Control in hardware.
But, it is strongly recommended that you hardcode both of your Control Units in two separate ROMs.

Description:

  1. Build a simulation of Fig. 5.24
    Your simulation must support the following instructions
        add, addi, sub, addu, and, or, slt, sltu, lw, sw, beq, j, lui

  2. You must include the 3rd port on the Register File for debugging.

  3. Control Unit and ALU control
    You must create these two controls as two separate modules.
    You are not allowed to increase the size of ALUop; keep it as 2 bits.
    You are not allowed to use the ALUop == 3 for any reason.

  4. Control Unit Documentation
    Your control must use the signal names on Fig. 5-24.
  5. Shifters
    You may not use any gates or logic to implement the Shift left 2 operations.
    The shifts can be done solely with proper wiring.

  6. Testing
    Your cpu must execute both test programs correctly.

Deliverables:
  1. A formal, professional lab submission.
  2. Professional source code (will have large impact on lab grade)
    1. include all files whether you wrote them or not
    2. sort listings by file name (.h followed by .c for each file)
    3. code meets coding standards, especially overview standards
    4. A demo in lab on Feb. 26 or Feb. 28

Last updated on 2/17/08