CPE 315
Winter 2008
Lab #4 FAQ
- How do I see inside RAM?
You can use the same technique as for the register file but
it's not necessary.
The test program will load all results from memory to a register;
you can verify results in the register file.
- Which instructions does the control unit in Appendix C support?
This control unit is only partially complete. Its purpose is to show
you how to build a control unit from PLAs.
- Do we have to support negative offsets in the LW/SW?
Yes.
- How big should Data memory be?
Big enough to run the test program and no bigger.
Note that the Ram address bus must be exactly == log 2 Ram size
- How about some hints on designing the instructions that aren't
part of Fig. 5.24?
- ADDI
Control decodes the ADDI instruction and sets the control bits
appropriately.
Be sure to choose a clever ALUOp value (not 11)
- LUI
The design was done in lecture on Feb. 21.
- SLTU
The design was done in Lab Exercise #5
- What is the geometry of the Control ROM?
Input: 6 bits (less if you minimize). Do not send additional input
signals to Control!
Output: 16 bits, some unused
Size: 64 words (less if you minimize).
- What is the geometry of the ALU Control Rom?
Input: 8 bits or less (you should minimize). Do not send
additional signals to ALU Control! (such as Op Code)
Output: 5 bits, including SLTU (declare an 8 bit bus and leave 3 unused)
Size: 256 words if you're crazy enough not to minimize
- What's the difference between ADD and ADDU?
For this lab, there is no difference.
In a MIPS cpu, an overflow during an ADD will generate an exception.
- Can we use the unused code in ALUOp (11)?
No. It complicates the design, isn't necessary and is explicitly disallowed.
- What SIM component should be used for Data Memory?
RAM. There is an example usage in the SIM apis.
Watch out for the preconditions!
- The J loop instruction in the test program appears incorrect.
It is correct. Recall the two zeroes that must be appended to the address.
So the J jumps to address 0x10 == loop.
Last updated on 2/27/08