CPE 315
Winter 2008
Professor Stearns
Lab #6 FAQ

1. Can I create two MMUs, one for each memory?
   No. You must design one MMU module and instantiate it twice.
   This design is much better than trying to work with one MMU object.

2. Do we have to worry about exceptions?
   No. Assume the program generates no exceptions; it doesn't.
   The Lab 6 descriptor contains the P and V bits for learning purposes only - you don't need to process exceptions.
   Be sure to use only bits 5-0 when you do the address translation.
   

3. How big is the bus that leaves the MMU?
   These must be exactly:
   

   8 bits for the data memory.
   9 bits for the instruction memory.
   

   Note that the Ram and Rom are both word-addressable devices; they expect a word (not a byte) address.
   e.g. if you put a 4 on the address bus, it accesses MIPS address 16.
   

4. I'm confused; there are two MMUs and one page table?
   Look at the memory allocation tables at the bottom of the lab; the page frame allocations for pages 0 and 14 are identical.
   Therefore you can use the same page table; this isn't realistic but greatly simplifies the lab.

5. What happened to pages 1 and 2 in the data address space?
   Look at the code; the only data pages are 0 and 14.

6. What are the bus sizes entering/leaving the MMU?
   The instruction memory MMU takes the 32 bit PC as input and outputs the 9 bit word address that contains the instruction.
   e.g. In the first fetch (PC = 0x00000008) the MMU translates the PC to memory address 0x308.
   The word address of 0x308 is 0x0C2, the address sent to the instruction memory.