Question 1 <br>
<ol type=a>
<li> It is impossible to fit an address into an instruction
since both are 32 bits. <br>
Be prepared to implement la on the final exam using 64 bits for the
instruction. <br>
<li> ISAs are much more complicated and compilers have improved; they now produce better code than excellent programmers. <br>
See Chapter 2 fallacies on page 144  <br>
<li> Approximately, but not exactly, 6.666. <br>
Floating point numbers are approximations so the addition can't be accurate. 
<li> Every instruction has the same speed - the speed of the slowest 
instruction.  <br>
There are two separate memories; this violates the basic stored-program
 principle on page 145.   <br>
<li> Exception causes a context switch where: <br>
PC = 0x80000180 <br>
EPC = address of instruction when exception occurred <br>
Cause = type of exception
</ol>
<p>
Question #2 <br>
The fetch, address computation and memory read  work exactly like the lw; 
see Figure 5.20  <br>
The word from Read data must go to the PC instead of  Registers Write data
port. <br>
So expand the Jump mux to 4 inputs; the 3rd input comes from Read data. <br>
The Jump mux needs a new select line (JM) <br>
<p>
Question #3 <br>
This was taken directly from Homework #3. <br>
Prepare for lots of arithmetic questions on the final exam - worth many points. <br>
<pre>
# The sum < both operands if there is a carry 
# Perform the addition
addu $t2,$t4,$t5

# Carry = 1 if $t2 < $t4
sltu $t6,$t2,$t4

# Return
jr $ra 
</pre>
<p>

Question #4 <br>
<ol type=a>
<li> The jump can jump much farther than the beq: 28 bits versus 18 bits  <br>
<li> 
<pre>
    lui $2, ADDR/65536
    ori $2, $2, ADDR*65536/65536
    jr  $2
</pre>
<li> 0x10000003 <br>
</ol>
<p>

Question #5 <br>
22.375 = 10110.011 = 1.0110011 x 2 <sup> 4 </sup> <br>
Exponent = 4 + 127 = 0x83 = 10000011 <br>
Float = 0 10000011 011001100...0000  = 0x41B30000 <br>
<p>

Question #6 <br>
Figure 5.30 for R-type instructions shows the data path used. <br>
slt requires 4 clocks. <br>
<p>

<table border>
<tr>
<th> Control Signal </th>
<th> Decode Step</th>
<th> Execution Step </th>
</tr>

<tr>
<td> ALUSrcB </td>
<td> 11 </td>
<td> 00 </td>
</tr>

<tr>
<td> ALUSrcA </td>
<td> 0 </td>
<td> 1 </td>
</tr>

<tr>
<td> RegDst</td>
<td> X </td>
<td> X </td>
</tr>

<tr>
<td> ALU Control lines </td>
<td> 0010 </td>
<td> 0111 </td>
</tr>


</table>
<p>


Question #7 <br>
<ol type=a>
<li> Kidder nevers explicitly states the reason but infers:  <br>
To teach the team to be self sufficient and resourceful. <br>
To protect the team from DG politics. <br>
<li> To speed up the cpu. 
<li> Some recompiled Eclipse programs might not run on the Eagle. Some would.
<br>
This is a code port problem;  customers don't want to port their code 
for the many reasons we discussed in class.  <br>
The Data General customers expected to run their Eclipse programs on the
Eagle without doing any port work.  <br>
<li> You can make cpu design changes (both in development and in the field) 
without changing any circuits. <br>
You can write emulators. <br>
<li> The whole purpose of the project was 32 bithood - a machine with a
32 bit address space. <br>
So Wallach had to start with the address space decision. <br>
Note for final:  he had one other absolute requirement - no mode bit. <br>
<li> They thought the kids would know more than them. <br>
They believed the kids wouldn't be limited by past experience. <br>
<li> The team was disbanded by Data General and most of the team 
quit the company. <br>
They felt unappreciated. <br>

</ol>
<p>

Question #8 <br>
<pre>
   0110000   = 0x30
-     0110   = 0x06
               ----
               0x2A  
</pre>
<p>

Question #9 <br>
5-39 control requires a state machine to determine which clock step
is running. <br>
A state machine cannot be implemented in a ROM. <br>
MIPS control is implemented with a microsequencer (a simple cpu) 
that executes a program (microprogram) to generate the control signals. <br>
<p>