A Comparison of Superscalar and Decoupled Access/Execute
Architectures
Matthew Farrens, Pius Ng, and Phillip Nico
Department of Computer Science
University of California, Davis
Davis, CA 95616
Abstract
This paper presents a comparison between superscalar and decoupled
access/execute architectures. Both architectures attempt to exploit
instruction-level parallelism by issuing multiple instructions per cycle,
employing dynamic scheduling to maximize performance.
Simulation results are presented for four different configurations,
demonstrating that the architectural queues of the decoupled machines
provide similar functionalities as register renaming, dynamic loop
unrolling, and out-of-order execution of the superscalar machines with
significantly less complexity.
Full paper
Appears in
Proceeding of the
Twenty-sixth Annual International Symposium on Microarchitecture,
December 1993.