Caching in on Sisal: Cache performance of Sisal vs. Fortran
Phillip Nico and Arvin Park
Department of Computer Science
University of California, Davis
Davis, CA 95616
Abstract
In this paper we investigate the relative cache performance of SISAL
and FORTRAN through trace-driven simulation of representative
scientific applications. The rance of cache configurations considered
corresponds to on-chip caches in current and next-generation
microprocessors. We find that in unified caches the performance is
equivalend. With split instruction and data caches, performance is
still comparable, yet the two languages demonstrate somewhat different
tendencies.
Full paper
Appears in
Proceedings of Sisal '93,
San Diego, California, October 1993.